In today's nanometer circuit design, it is almost standard practice by including power network in the timing simulation or timing analysis. Due to complexity in combining circuit and power network in calculating voltage drop or surge is very cumbersome. Very often the two-stage approach, namely the first stage of calculating power currents at the contact points, and the second stage in obtaining voltage drop by utilizing the said power currents injected into the power network through the said contact points, is adopted. As to the second stage in evaluating the voltage drop, it can be very CPU intensive to run circuit simulation on extremely large power network. Therefore, how to solve power network efficiently poses a challenging task.
It is well-known that the traditional spice-in-spice-out approach based on RC reduction method which reduces the original power network into a smaller circuit still in spice format has been adopted for quite a few years. The beauty of this approach is that it does reduce the power network and the reduced circuit in spice format can be immediately accepted by any timing simulator without any change of existing simulation engine. However, there are several deficiencies. First, in this spice-in-spice-out approach some internal nodes of power network in some cases may need to be saved for other purposes, but they turn out to be deleted after RC reduction. Secondly, there is an accuracy issue. RC reduction most often reduce a line of resistors into a single one with sensible resistance and capacitance values. If the size of sub-networks tends to be large, the accuracy may be degraded. Thirdly, to achieve better partition result, the partition size should be as large as possible without increasing the number of internal nodes of the reduced power network. However, large sub-network with many ports are not possible to be reduced into a simple circuit.
This invention proposes a novel method to reduce power network by saving the specified nodes with minimal performance penalty based on admittance matrix and voltage transfer in frequency domain calculated by using well-known methods such as AWE (asymptotic waveform expansion) and reduced ordering methods. It is worthwhile to point out that interconnect for power network is treated quite differently from the routing signals. The reason is that routing signals tend to have one or several inputs in case of cross-talk, while power network has a huge number of inputs which are the contacts of power network. Therefore, it is not possible to calculate the extremely large admittance matrix since matrix size is the same as the huge number of inputs of power network. The concept of partitioning the power network has been quite well-known for years. However, to generate sensible RC reduced circuit, namely, both resistance and capacitance are positive numbers, still the lowest order in frequency domain is adopted, meaning each partition of the whole power network must be small in order to preserve accuracy. Note that by means of reduced ordering approach through congruence transformation the reduced circuit may be generated, but with wildly negative capacitance and resistance. Besides, by saving some internal nodes the partition result can be affected.
With all of the deficiencies as stated above for the traditional approach this invention proposes novel approach in three steps to solve voltage drop of power network in an efficient approach without compromise of accuracy. The first part lies in the step of partitioning the power network by recognizing its inputs and outputs. While decomposing the circuit into tree structure with strongly connected components (SCC) can be found in any standard textbook, the actual implementation involves the algorithms to enlarge partition size without increasing the number of nodes for the reduced power network. These algorithms include identifying output network with one input and outputs and sub-network without input and output and regardless of any resistor connected to power source. The second step deals with the calculation of admittance matrix for the inputs of each sub-network after partition, plus voltage transfer by treating specified nodes to be saved as output nodes in the sub-network, without the need to transform these said admittance matrix and voltage transfer into an equivalent circuit with positive resistance and capacitance values, the step of which in some cases is impossible to be achieved. Finally the third step is to perform timing simulation in time and frequency domain by integrating the reduced power network in frequency domain in terms of admittance matrix and voltage transfer into circuit in time domain. In this invention the timing simulation engine is enhanced to handle both admittance matrix and voltage transfer in the same simulation engine at each time step with very minimal overhead in CPU.